1. Field of the Invention
This invention relates to semiconductor memory and, more particularly, to a memory interface that transparently separates the read and write address and data buses to achieve a faster sequential read and write cycle time.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art or conventional by virtue of their inclusion within this section.
Most computing systems consist of four functional blocks: a microprocessor (or CPU), memory, input/output (I/O) interface, and an I/O device. The CPU is interconnected to the memory and the I/O interface via an address bus and a data bus. The address bus provides a path in which the CPU can select certain storage locations in which data is stored. The data bus provides a path over which data is transferred between the CPU, memory, and the I/O interface. Most microprocessors handle bits in 16, 32, or 64 bit groups. Thus, the address bus and data bus are normally 16, 32, or 64 bits wide.
The mechanism by which a CPU or I/O interface accesses memory depends on the type of memory being accessed. There are numerous types of memories available in the marketplace. For example, data can be stored in magnetic memory, such as a hard disk drive, or stored in memory elements upon an integrated circuit, sometimes referred to as “semiconductor memory.” Semiconductor memory is typically arranged closer to the CPU or execution unit than a hard disk drive and, therefore, can be accessed much faster than magnetic memory.
Common to semiconductor memory is an array of storage elements. Depending on the type of semiconductor memory, each storage element can have a significantly different architecture and function. For example, a storage element can be volatile or non-volatile. Types of volatile memory include memory that must be periodically refreshed (DRAMs) or memory that will lose its programmed state if power is removed (SRAMs).
The differences between SRAMs and DRAMs are fairly significant. Each storage element of SRAM includes latch and pass transistors. Conversely, each cell of DRAM involves simply one transistor and a capacitive storage element. While DRAMs are significantly denser than SRAMs, DRAMs require additional support circuitry to coordinate the accesses of each element, along with the need to periodically refresh that element.
SRAMs typically implement complementary bit lines and bit line signals and enjoy the benefits of faster access times than DRAMs. SRAMs are oftentimes used as the primary cache of the CPU, whereas DRAMs are generally used as the main semiconductor memory. SRAM has a faster access time than DRAM since performance of a read operation simply involves asserting an address, asserting a chip select line, and a read/write enable signal. The requested data will then appear sometime thereafter upon the data lines.
As used herein, the term “access time” for a read operation, for example, is the time between when an address is placed on the address bus and the addressed data appears on the data bus. Access time often gauges the speed of the memory, which is the time from assertion of a valid address to valid data (read operation), or to completion of the write into the array (write operation).
Even with fast access time associated with SRAM, one memory access cannot be rapidly followed by another memory access. The time from one memory access to the next is often referred to as the “cycle time.” For SRAM, cycle time is generally equal to the access time. Therefore, in an SRAM, a write operation must wait until the read operation has completed before the write operation can begin. This is due primarily to the address bus and data bus needing to be free of the previous operation before new addresses and data are presented on those respective buses. The problem of having a cycle time constraint on conventional SRAM is made more profound with the advent of newer double data rate (DDR) SRAM.
DDR memory allows data to be captured at a rate of twice the frequency of the clock signal sent along the control bus. This is accomplished by utilizing a 2n prefetch architecture, where the internal data bus of the DDR memory is twice the “n” width of the external data bus to allow data capture of twice per system clock cycle. A special form of DDR, when implementing both read and write accesses during the same cycle is referred to as quad data rate (QDR) SRAM. Under QDR transfer mechanisms, the internal data bus allows external data to be captured at four times per system clock cycle. Details of the difference between single data rate (SDR) and DDR, and the ramifications for QDR memories can be found in “General DDR SDRAM Functionality,” Micron Technology, 2001 (herein incorporated by reference).
While both SDR and QDR memory devices generally include the same array of storage elements, the input/output memory interface is considerably different. For example, QDR utilizes a differential pair of system clock signals to formulate the triggering rising and falling clock edges, and data strobe signals are needed to drive the data signal to and from the QDR-accessed memory banks. The differential system clock signals and the data strobe signals can allow accesses to occur and data to be strobed every one-half cycle of the system clock. Data throughput can, therefore, be substantially increased at a 2× factor.
While it would be beneficial to implement QDR SRAM with faster access time than DRAM, it would also be beneficial to reduce the cycle time between accesses. A desired solution should be one that can implement QDR SRAM accesses, but with subsequent accesses occurring partially concurrent with the previous accesses in order to reduce the cycle time, and therefore take full advantage of a high-speed system clock implemented in a QDR methodology.